/*

 $Id: DS31256_regs.h 4 2009-09-18 02:22:01Z alex.mobilebi $
 $Date: 2009-09-18 02:22:01 +0000 (Fri, 18 Sep 2009) $
 $Author: alex.mobilebi $
 $Revision: 4 $

 Copyright(C) 2009 Alex Lee(alex@mobilebi.com)

 */

#ifndef NV_DS31256_REGS_H
#define NV_DS31256_REGS_H

/* Definition of DS31256's General Configuration Registers(0xx) */
#define DS31256_GCR_MRID         0x0000       /* Master Reset and ID Register */
#define DS31256_GCR_MC           0x0010       /* Master Configuration */
#define DS31256_GCR_SM           0x0020       /* Master Status Register */
#define DS31256_GCR_ISM          0x0024       /* Interrupt Mask Register for SM */
#define DS31256_GCR_SDMA         0x0028       /* Status Register for DMA */
#define DS31256_GCR_ISDMA        0x002C       /* Interrupt Mask Register for SDMA */
#define DS31256_GCR_SV54         0x0030       /* Status Register for V.54 Loopback Detector */
#define DS31256_GCR_ISV54        0x0034       /* Interrupt Mask Register for SV.54 */
#define DS31256_GCR_LBBMC        0x0040       /* Local Bus Bridge Mode Control Register */
#define DS31256_GCR_TEST         0x0050       /* Test Register */
                                                                                                              
/* Definition of DS31256's Receive Port Registers(1xx) */                                                     
#define DS31256_RPR_RP0CR        0x0100       /* Receive Port 0 Control Register */
#define DS31256_RPR_RP1CR        0x0104       /* Receive Port 1 Control Register */
#define DS31256_RPR_RP2CR        0x0108	      /* Receive Port 2 Control Register */
#define DS31256_RPR_RP3CR        0x010C	      /* Receive Port 3 Control Register */
#define DS31256_RPR_RP4CR        0x0110	      /* Receive Port 4 Control Register */
#define DS31256_RPR_RP5CR        0x0114	      /* Receive Port 5 Control Register */
#define DS31256_RPR_RP6CR        0x0118	      /* Receive Port 6 Control Register */
#define DS31256_RPR_RP7CR        0x011C	      /* Receive Port 7 Control Register */
#define DS31256_RPR_RP8CR        0x0120	      /* Receive Port 8 Control Register */
#define DS31256_RPR_RP9CR        0x0124	      /* Receive Port 9 Control Register */
#define DS31256_RPR_RP10CR       0x0128	      /* Receive Port 10 Control Register */
#define DS31256_RPR_RP11CR       0x012C	      /* Receive Port 11 Control Register */
#define DS31256_RPR_RP12CR       0x0130	      /* Receive Port 12 Control Register */
#define DS31256_RPR_RP13CR       0x0134	      /* Receive Port 13 Control Register */
#define DS31256_RPR_RP14CR       0x0138	      /* Receive Port 14 Control Register */
#define DS31256_RPR_RP15CR       0x013C	      /* Receive Port 15 Control Register */
                                                                                                              
/* Definition of DS31256's Transmit Port Registers(2xx) */                                                    
#define DS31256_TPR_TP0CR        0x0200       /* Transmit Port 0 Control Register */
#define DS31256_TPR_TP1CR        0x0204       /* Transmit Port 1 Control Register */
#define DS31256_TPR_TP2CR        0x0208       /* Transmit Port 2 Control Register */
#define DS31256_TPR_TP3CR        0x020C       /* Transmit Port 3 Control Register */
#define DS31256_TPR_TP4CR        0x0210       /* Transmit Port 4 Control Register */
#define DS31256_TPR_TP5CR        0x0214       /* Transmit Port 5 Control Register */
#define DS31256_TPR_TP6CR        0x0218       /* Transmit Port 6 Control Register */
#define DS31256_TPR_TP7CR        0x021C       /* Transmit Port 7 Control Register */
#define DS31256_TPR_TP8CR        0x0220       /* Transmit Port 8 Control Register */
#define DS31256_TPR_TP9CR        0x0224       /* Transmit Port 9 Control Register */
#define DS31256_TPR_TP10CR       0x0228       /* Transmit Port 10 Control Register */
#define DS31256_TPR_TP11CR       0x022C       /* Transmit Port 11 Control Register */
#define DS31256_TPR_TP12CR       0x0230       /* Transmit Port 12 Control Register */
#define DS31256_TPR_TP13CR       0x0234       /* Transmit Port 13 Control Register */
#define DS31256_TPR_TP14CR       0x0238       /* Transmit Port 14 Control Register */
#define DS31256_TPR_TP15CR       0x023C       /* Transmit Port 15 Control Register */
                                                                                                              
/* Definition of DS31256's Channelized Port Registers (3xx) */                                                
#define DS31256_CPR_CP0RDIS      0x0300       /* Channelized Port 0 Register Data Indirect Select */ 
#define DS31256_CPR_CP0RD        0x0304       /* Channelized Port 0 Register Data */   
#define DS31256_CPR_CP1RDIS      0x0308       /* Channelized Port 1 Register Data Indirect Select */ 
#define DS31256_CPR_CP1RD        0x030C       /* Channelized Port 1 Register Data */   
#define DS31256_CPR_CP2RDIS      0x0310       /* Channelized Port 2 Register Data Indirect Select */ 
#define DS31256_CPR_CP2RD        0x0314       /* Channelized Port 2 Register Data */   
#define DS31256_CPR_CP3RDIS      0x0318       /* Channelized Port 3 Register Data Indirect Select */ 
#define DS31256_CPR_CP3RD        0x031C       /* Channelized Port 3 Register Data */   
#define DS31256_CPR_CP4RDIS      0x0320       /* Channelized Port 4 Register Data Indirect Select */ 
#define DS31256_CPR_CP4RD        0x0324       /* Channelized Port 4 Register Data */   
#define DS31256_CPR_CP5RDIS      0x0328       /* Channelized Port 5 Register Data Indirect Select */ 
#define DS31256_CPR_CP5RD        0x032C       /* Channelized Port 5 Register Data */   
#define DS31256_CPR_CP6RDIS      0x0330       /* Channelized Port 6 Register Data Indirect Select */ 
#define DS31256_CPR_CP6RD        0x0334       /* Channelized Port 6 Register Data */        
#define DS31256_CPR_CP7RDIS      0x0338       /* Channelized Port 7 Register Data Indirect Select */ 
#define DS31256_CPR_CP7RD        0x033C       /* Channelized Port 7 Register Data */   
#define DS31256_CPR_CP8RDIS      0x0340       /* Channelized Port 8 Register Data Indirect Select */
#define DS31256_CPR_CP8RD        0x0344       /* Channelized Port 8 Register Data */ 
#define DS31256_CPR_CP9RDIS      0x0348       /* Channelized Port 9 Register Data Indirect Select */
#define DS31256_CPR_CP9RD        0x034C       /* Channelized Port 9 Register Data */ 
#define DS31256_CPR_CP10RDIS     0x0350       /* Channelized Port 10 Register Data Indirect Select */
#define DS31256_CPR_CP10RD       0x0354       /* Channelized Port 10 Register Data */
#define DS31256_CPR_CP11RDIS     0x0358       /* Channelized Port 11 Register Data Indirect Select */
#define DS31256_CPR_CP11RD       0x035C       /* Channelized Port 11 Register Data */
#define DS31256_CPR_CP12RDIS     0x0360       /* Channelized Port 12 Register Data Indirect Select */
#define DS31256_CPR_CP12RD       0x0364       /* Channelized Port 12 Register Data */
#define DS31256_CPR_CP13RDIS     0x0368       /* Channelized Port 13 Register Data Indirect Select */
#define DS31256_CPR_CP13RD       0x036C       /* Channelized Port 13 Register Data */
#define DS31256_CPR_CP14RDIS     0x0370       /* Channelized Port 14 Register Data Indirect Select */
#define DS31256_CPR_CP14RD       0x0374       /* Channelized Port 14 Register Data */
#define DS31256_CPR_CP15RDIS     0x0378       /* Channelized Port 15 Register Data Indirect Select */
#define DS31256_CPR_CP15RD       0x037C       /* Channelized Port 15 Register Data */
                                                                                                              
/* Definition of DS31256's HDLC Registers (4xx) */                                                            
#define DS31256_HDLC_RHCDIS      0x0400       /* Receive HDLC Channel Definition Indirect Select */
#define DS31256_HDLC_RHCD        0x0404       /* Receive HDLC Channel Definition */
#define DS31256_HDLC_RHPL        0x0410       /* Receive HDLC maximum Packet Length. One per device */
#define DS31256_HDLC_THCDIS      0x0480       /* Transmit HDLC Channel Definition Indirect Select */
#define DS31256_HDLC_THCD        0x0484       /* Transmit HDLC Channel Definition */    
                                                                                                              
/* Definition of DS31256's BERT Registers (5xx) */                                                            
#define DS31256_BERT_BERTC0      0x0500       /* BERT Control 0 */
#define DS31256_BERT_BERTC1      0x0504       /* BERT Control            */
#define DS31256_BERT_BERTRP0     0x0508       /* BERT Repetitive Pattern Set 0 (lower word) */
#define DS31256_BERT_BERTRP1     0x050C       /* BERT Repetitive Pattern Set 1 (upper word) */
#define DS31256_BERT_BERTBC0     0x0510       /* BERT Bit Counter 0 (lower word) */
#define DS31256_BERT_BERTBC1     0x0514       /* BERT Bit Counter 1 (upper word) */
#define DS31256_BERT_BERTEC0     0x0518       /* BERT Error Counter 0 (lower word) */
#define DS31256_BERT_BERTEC1     0x051C       /* BERT Error Counter 1 (upper word) */
                                                                                                              
/* Definition of DS31256's Receive DMA Registers (7xx) */                                                     
#define DS31256_RDMA_RFQBA0      0x0700       /* Receive Free-Queue Base Address 0 (lower word) */                                 
#define DS31256_RDMA_RFQBA1      0x0704       /* Receive Free-Queue Base Address 1 (upper word) */ 
#define DS31256_RDMA_RFQEA       0x0708       /* Receive Free-Queue End Address */ 
#define DS31256_RDMA_RFQSBSA     0x070C       /* Receive Free-Queue Small Buffer Start Address */ 
#define DS31256_RDMA_RFQLBWP     0x0710       /* Receive Free-Queue Large Buffer Host Write Pointer */ 
#define DS31256_RDMA_RFQSBWP     0x0714       /* Receive Free-Queue Small Buffer Host Write Pointer */ 
#define DS31256_RDMA_RFQLBRP     0x0718       /* Receive Free-Queue Large Buffer DMA Read Pointer */ 
#define DS31256_RDMA_RFQSBRP     0x071C       /* Receive Free-Queue Small Buffer DMA Read Pointer */ 
#define DS31256_RDMA_RDQBA0      0x0730       /* Receive Done-Queue Base Address 0 (lower word) */ 
#define DS31256_RDMA_RDQBA1      0x0734       /* Receive Done-Queue Base Address 1 (upper word) */   
#define DS31256_RDMA_RDQEA       0x0738       /* Receive Done-Queue End Address */   
#define DS31256_RDMA_RDQRP       0x073C       /* Receive Done-Queue Host Read Pointer */   
#define DS31256_RDMA_RDQWP       0x0740       /* Receive Done-Queue DMA Write Pointer */   
#define DS31256_RDMA_RDQFFT      0x0744       /* Receive Done-Queue FIFO Flush Timer */   
#define DS31256_RDMA_RDBA0       0x0750       /* Receive Descriptor Base Address 0 (lower word) */   
#define DS31256_RDMA_RDBA1       0x0754       /* Receive Descriptor Base Address 1 (upper word) */   
#define DS31256_RDMA_RDMACIS     0x0770       /* Receive DMA Configuration Indirect Select */   
#define DS31256_RDMA_RDMAC       0x0774       /* Receive DMA Configuration */   
#define DS31256_RDMA_RDMAQ       0x0780       /* Receive DMA Queues Control */   
#define DS31256_RDMA_RLBS        0x0790       /* Receive Large Buffer Size */ 
#define DS31256_RDMA_RSBS        0x0794       /* Receive Small Buffer Size */ 
                                                                                                              
/* Definition of DS31256's Transmit DMA Registers (8xx) */                                                  
#define DS31256_TDMA_TPQBA0      0x0800       /* Transmit Pending-Queue Base Address 0 (lower word) */ 
#define DS31256_TDMA_TPQBA1      0x0804       /* Transmit Pending-Queue Base Address 1 (upper word) */ 
#define DS31256_TDMA_TPQEA       0x0808       /* Transmit Pending-Queue End Address */ 
#define DS31256_TDMA_TPQWP       0x080C       /* Transmit Pending-Queue Host Write Pointer */ 
#define DS31256_TDMA_TPQRP       0x0810       /* Transmit Pending-Queue DMA Read Pointer */ 
#define DS31256_TDMA_TDQBA0      0x0830       /* Transmit Done-Queue Base Address 0 (lower word) */ 
#define DS31256_TDMA_TDQBA1      0x0834       /* Transmit Done-Queue Base Address 1 (upper word) */ 
#define DS31256_TDMA_TDQEA       0x0838       /* Transmit Done-Queue End Address */ 
#define DS31256_TDMA_TDQRP       0x083C       /* Transmit Done-Queue Host Read Pointer */ 
#define DS31256_TDMA_TDQWP       0x0840       /* Transmit Done-Queue DMA Write Pointer */ 
#define DS31256_TDMA_TDQFFT      0x0844       /* Transmit Done-Queue FIFO Flush Timer */ 
#define DS31256_TDMA_TDBA0       0x0850       /* Transmit Descriptor Base Address 0 (lower word) */ 
#define DS31256_TDMA_TDBA1       0x0854       /* Transmit Descriptor Base Address 1 (upper word) */ 
#define DS31256_TDMA_TDMACIS     0x0870       /* Transmit DMA Configuration Indirect Select */
#define DS31256_TDMA_TDMAC       0x0874       /* Transmit DMA Configuration */ 
#define DS31256_TDMA_TDMAQ       0x0880       /* Transmit DMA Queues Control */  
                                                                                                              
/* Definition of DS31256's FIFO Registers (9xx) */                                                            
#define DS31256_FIFO_RFSBPIS     0x0900       /* Receive FIFO Starting Block Pointer Indirect Select */     
#define DS31256_FIFO_RFSBP       0x0904       /* Receive FIFO Starting Block Pointer */     
#define DS31256_FIFO_RFBPIS      0x0910       /* Receive FIFO Block Pointer Indirect Select */     
#define DS31256_FIFO_RFBP        0x0914       /* Receive FIFO Block Pointer */     
#define DS31256_FIFO_RFHWMIS     0x0920       /* Receive FIFO High-Watermark Indirect Select */     
#define DS31256_FIFO_RFHWM       0x0924       /* Receive FIFO High Watermark */     
#define DS31256_FIFO_TFSBPIS     0x0980       /* Transmit FIFO Starting Block Pointer Indirect Select */     
#define DS31256_FIFO_TFSBP       0x0984       /* Transmit FIFO Starting Block Pointer */     
#define DS31256_FIFO_TFBPIS      0x0990       /* Transmit FIFO Block Pointer Indirect Select */     
#define DS31256_FIFO_TFBP        0x0994       /* Transmit FIFO Block Pointer */     
#define DS31256_FIFO_TFLWMIS     0x09A0       /* Transmit FIFO Low-Watermark Indirect Select */    
#define DS31256_FIFO_TFLWM       0x09A4       /* Transmit FIFO Low Watermark */  

#endif

